Samsung Electronics plans to complete the development of 3D Cube-H in early 2027

Samsung Electronics plans to complete the development of advanced packaging technology 3D Cube-H by early 2027 and finish the first design kit, followed by evaluations with potential customers. This technology achieves vertical stacking of chips based on hybrid bonding, primarily targeting high-performance AI semiconductors, which can be used to stack logic chips such as GPUs or integrate logic chips on memory chips like HBM.

Samsung Electronics has previously developed 3D Cube-T using thermocompression bonding technology and is currently advancing 3D Cube-H with a terminal pitch of about 6 micrometers, while the minimum terminal pitch for thermocompression bonded chips is about 25 micrometers. Hybrid bonding connects copper materials directly between chips, allowing for reduced terminal pitch, increased connection density, and lower energy consumption per bit, with thermal characteristics that differ from thermocompression bonding solutions.